The present invention relates to a semiconductor device, in particular, to a technology effective when applied to a semiconductor device having CMOS or SRAM on an SOI substrate.
SRAM (Static Random Access Memory) is a kind of semiconductor memories and it stores data by using flip flop. For example, in SRAM, data (“1” or “0”) is stored in two cross-coupled CMOS inverters comprised of four transistors. In addition, it needs two transistors for read and write accesses so that in a typical SRAM, a memory cell has six transistors. CMOS is an abbreviation of Complementary MOS (Metal Oxide Semiconductor).
For example, Patent Document (International Patent Publication WO/2010/082504) discloses a technology of reducing an element area of an SOI-MISFET excellent in low power consumption and high speed operation. Described specifically, according to the technology disclosed in this document, an N conductivity type MISFET region and a P conductivity type MISFET region in an SOI type MISFET are formed to share a diffusion layer region and respective well-region diffusion layers of the N conductivity type MISFET region and the P conductivity type MISFET region which apply a substrate potential thereto are isolated from each other by an STI layer. For example, it is disclosed that threshold voltage control diffusion layer regions (25) and (26) shown in FIG. 15 and paragraph [0037] are electrically coupled to an outside line, for example, power source supply line. The number in the parentheses shows the reference number described in the above document.
[Patent Document 1] International Patent Publication WO/2010/082504